A signal buffer that inserts essentially no additional propagation delay in the signal path is required for many applications. A phase locked loop (PLL) or delay locked loop (DLL) based zero delay buffer can address the requirement for essentially no additional propagation delay. A continuous clock, even in the event of loss of a reference signal, is also required for many applications.
Conventional timing systems can result in problems, for example, when used in communications systems that derive timing from incoming data streams. Loss of the data stream (due to storm, interference, etc.) can result in loss of circuit timing generation unless a backup timing source is available.
Conventional timing circuits can use backup reference oscillators to compensate for the loss of the primary timing reference. Conventional backup reference oscillators have multiplexers with external control logic to select between the primary and secondary (backup) reference oscillator where both the primary and secondary reference oscillator are located “off-chip”. However, conventional technology has the following disadvantages:                (i) external control circuitry is required to control the reference selection multiplexer, (ii) the secondary reference is not phase aligned with the primary reference, (iii) a change from the primary reference to the secondary reference and back can result in an interruption of the clock, and/or (iv) a secondary reference source is required.        
It would be desirable to have a zero delay buffer circuit that (i) has a reference oscillator phase aligned with a primary reference oscillator and (ii) automatically provides an internal reference clock if the primary reference stops.